What was reviewed
The primary competitor source is /home/verilog/lssk_claude/breadboard, not an older archived session. The comparison source is the current /home/verilog/lssk_codex/breadboard. The two copies of 20261019_exercise.md are identical. Both directories were snapshotted; SHA-256 manifest records the reviewed files.
The audit covers both languages, all HDL, simulator scripts, pinouts, three schematics, state and timing diagrams, parts and wiring tables, BGM/Tiny Tapeout examples, local links, JavaScript and generator structure. Relevant generators outside Claude’s breadboard directory were inspected too. No original competitor file was edited.
Style is compared against your current rules, including yuri_rules_3.txt. Claude’s visible yuri_rules_4.txt contains only the delay/falling-edge guidance; the audit does not assume it received every later Codex instruction. Style gaps are separated from functional defects.
Limits: no physical breadboard, FPGA programming or ASIC implementation was performed. Image assets were visually inspected. HTML and JavaScript received static/DOM-stub checks; full browser rendering, clipboard permissions and print output remain unverified. Exact Icarus 13 is unavailable; versions 12 and 14 were used.
Results actually reproduced
| Check | Result | Evidence and limit |
|---|
| Claude supplied bench | PASS: 82 checks in Icarus 12, Icarus 14 and Verilator 5.053. | Icarus 12 · Icarus 14 · Verilator |
| Claude cores with extended expected-state checks | PASS: 285 observations, 12 cycles, 48/24/48 color slots, reset at both levels and wrap. Only the bench port name state → q was adapted. | log · review bench |
| Claude chip models independently exercised | PASS: all 256 OR input vectors, 30 regular count edges, carry, inhibit and asynchronous reset. | log · review bench |
| Claude wrappers | Compile in Icarus and Questa. Reviewer simulation passes 30 states, both segment mappings, 8 state LEDs, 120 selected LCD pixels and TT input-only bidirectional pins. | log · review bench. This is not a full video-raster or FPGA test. |
| Codex supplied suite | All three benches pass Icarus 12/14 and Verilator. Core, standalone chip and both integration variants are tested. | validation.json |
| Wiring and generated content | Claude’s pin/wire checks pass and generated chip RTL matches its published file. All 9 embedded HDL blocks match files; both sites have no broken local links in their original workspace. | wiring · generator · HTML audit |
| Checklist JavaScript | PASS: initial count, checking a row, reload persistence, clearing, malformed storage and disabled-storage fallback. | DOM-stub evidence · check source |
Questa
Both source sets compile with Questa 2025.2 with zero errors/warnings under the checked commands. Runtime was attempted after locating the installed license. The license host ID matches a physical adapter, but FlexNet returns an empty host ID in this restricted execution environment. Console mode also fails to create its socket; batch mode reaches license checkout and reports Invalid host. No Questa runtime PASS is claimed for either project in this audit. Claude’s page states it was previously tested with Questa; that statement could not be independently reproduced here.
Claude compile log · environment diagnosis · runtime log. The Codex runner now discovers the installation and the existing license automatically and defaults to batch mode. From a normal licensed terminal:
cd /home/verilog/lssk_codex/breadboard/traffic_light
./scripts/run_questa.sh
The script requires PASS from each bench and fails if the design cannot load. The license file and its contents were not copied into any distributed artifact.
Specific problems and recommended corrections
These findings distinguish demonstrated errors, missing coverage, portability problems and presentation ambiguities. No failure of the normal reset/4-red/2-yellow/4-green sequence was found in either submitted implementation.
F01 · mediumImplicit time units make simulation traces nonportable
Confirmed portability problem. None of Claude’s nine HDL modules declares timeunit/timeprecision. The supplied Icarus run finishes at 445 seconds; Verilator finishes at 445 picoseconds. Both report the same logical PASS, so this is not a wrong 4/2/4 sequence. It is a real difference of 10¹² in the physical interpretation of simulation time. The BGM lab additionally inherits a legacy timescale through config.svh.
Correction: Add module-local timeunit 1ns; timeprecision 1ps; and regenerate the waveform with an explicit time axis. Preserve the current clock-event behavior.
Icarus log · Verilator log · tb.sv:11–61
F02 · mediumThe supplied test misses a low-clock reset defect
Confirmed coverage gap, not a defect in the submitted RTL. A mutant that accepts reset only while clk is high still reports PASS: 82 checks in Claude’s supplied bench. The adapted extended bench rejects it. Conversely, an ordinary synchronous-reset mutant is detected by Claude’s bench: FAIL with two errors. It would be incorrect to claim that Claude never checks asynchronous reset.
Correction: Keep the current pre-edge checker and add focused reset checks at both clock levels and from every state. A justified low-phase event is allowed by the user’s rules.
undetected mutant · extended test failure · synchronous-reset mutant
F03 · mediumNo watchdog; raw simulator failure exits successfully
Claude’s tb.sv has no cycle-counted timeout. Its final block prints FAIL without $fatal: the wrong-red and synchronous-reset mutants both return simulator exit code 0. The supplied shell scripts do catch this by requiring PASS, so their normal command-line workflow correctly fails. Direct simulator use or a different CI harness must not rely only on the process status.
Correction: Add a separate repeat (timeout_cycles) @ (posedge clk) watchdog and use $fatal for failed checks. Keep the script-level PASS check as a second check.
tb.sv:142–198 · process exit codes
F04 · mediumThe breadboard directory is not a complete offline handout
All local links resolve in Claude’s full workspace. However, both index pages link to ../exercises.html and the lesson links to ../../getting_started_en.html or ../../getting_started_ru.html. These four links leave breadboard/. The generators and source templates also live outside it. Copying only the requested directory loses the prerequisite instructions and rebuild tools.
Correction: Package the prerequisite pages and generator dependencies, or state the required repository layout explicitly. Codex already distributes a self-contained site ZIP and local rebuild tools.
local-link audit · site generator
F05 · mediumThe wiring proof assumes continuous power rails
Claude’s node_of() merges all positive rails into one node and all ground rails into another. That matches the depicted power module and an unsplit board, but does not prove that the remote 4072 is powered on a board with split rails. The separate getting-started page mentions split rails, yet the M11 checklist and its 24 M–M count include no bridge variant. Codex explicitly bridges rails, but its LP/LM/RP/RM numbering and split location are also a chosen board model, not a universal physical standard.
Correction: Identify the board’s actual rail continuity before assembly; provide a split-rail checklist variant and adjust quantities. Keep this a conditional hardware issue, not a claim that the shown circuit always fails.
bb_m11.py:178–186 · checked wire list · Codex rail bridges
F06 · mediumA statement about SystemVerilog wires is wrong
Section 9 says that a SystemVerilog wire simply has value 0 or 1. The default logic-valued wire is four-state: 0, 1, X and Z. The same lesson correctly shows unknown state before reset, which makes this sentence internally confusing. Omitting power pins means the model does not simulate electrical power; it does not make signals two-state.
Correction: Explain logical four-state simulation separately from voltage, current and power behavior.
lesson template:240–242
F07 · mediumASIC clock advice is too absolute
The heading “No clock divider on a chip” and the assertion that divided-clock delay is uncontrolled overstate a useful beginner recommendation. A clock-enable solution is appropriate here, but ASICs can use deliberately designed, constrained generated clocks. Related clock domains are not automatically asynchronous. OpenSTA explicitly supports defining clock dividers with create_generated_clock.
Correction: Say: for this exercise prefer one clock plus enable; derived clocks need deliberate clock-tree and timing-constraint design.
lesson template:351–358 · OpenSTA generated-clock documentation
F08 · mediumThe Johnson shortcut is valid only in reachable states
The three proposed lamp formulas are correct for all ten legal Johnson states. Exhaustive evaluation finds different outputs for all 22 other five-bit patterns. Therefore the claim that synthesis finds this optimization automatically needs a qualification: ordinary combinational simplification must preserve all input patterns unless reachability assumptions are established. The public q output also still requires a decoder.
Correction: Present it as a reset-dependent sequential optimization, prove equivalence on reachable states, and compare actual synthesis reports. It is a good extension exercise.
lesson template:384–389 · 32-pattern check and synthesis counts
F09 · mediumThe shortened-ring task gives an unjustified pulse duration
The Q8-to-RESET task says S8 lasts “a few nanoseconds”. That duration is not established by these zero-delay RTL models. The TI 5 V reset specification includes a 260 ns minimum external reset pulse width; a feedback pulse must be assessed using the actual chip timing and load. This does not prove the standard decoded-reset technique fails; it means the text must not promise an arbitrary pulse duration or treat the ideal HDL as its timing verification.
Correction: Use “a short transient determined by propagation delays”; add a datasheet or measured timing exercise.
lesson template:367–368 · TI CD4017B, page 1
F10 · lowStandalone state and timing diagrams need clearer labels
The state diagram says “every clock edge”, whereas the circuit advances on rising CLOCK edges with inhibit low. The surrounding prose is correct. The state circles encode lamp outputs only by color, and the simulation waveform has no numbered time axis or time unit. These are presentation ambiguities, not errors in the implemented transition sequence.
Correction: Label edges clk ↑, add R/Y/G values or text inside states, and add a time or cycle axis to the waveform. Retain the clear circular layout.
state diagram · waveform
Circuit, chip models and parts
The 4017 pin map and both OR-gate pin maps are correct in the inspected files and drawings. Both projects use the required OR groupings; using a different spare 4071 gate is electrically equivalent. Claude uses gate K, output pin 4, for yellow; Codex uses gate J, output pin 3. Unused inputs are tied to defined levels, and unused outputs are not shorted together. Tying unused CMOS gate inputs high in Claude’s layout is valid; it is not a mistake merely because Codex ties them low.
Claude’s five-bit Johnson implementation explains the chip’s internal idea more directly. Codex intentionally uses a ten-bit one-hot generic core and a four-bit binary functional chip model. These are different internal encodings of the same externally tested sequence. Neither model reproduces all physical power-up recovery or electrical timing behavior; both say reset is needed in simulation.
| Same synthesis flow: Yosys 0.69 + Slang | Flip-flops | Other mapped cells |
|---|
| Claude · traffic_light | 5 | 18 |
| Claude · traffic_light_chips | 5 | 18 |
| Codex · traffic_light | 10 | 7 |
| Codex · traffic_light_chips | 4 | 26 |
All four cores synthesize and pass check -assert. These are generic mapped cell counts with public state/decoded outputs retained, not chip area, power, FPGA resource utilization or timing measurements. A smaller register count does not establish the best implementation. Counts and logs.
Physical qualification remains shared unfinished work
- The chosen indicators have current limiting, but neither review run measured load current, output voltage or brightness. “5 V compatible” does not by itself establish a 4000B output-drive budget. Codex states this limit more explicitly; Claude presents direct drive more confidently.
- Use the actual module pin labels and verify the reset module’s released-low/pressed-high behavior. A bare pushbutton or ordinary LED is not automatically interchangeable with the specified module or current-limited indicator.
- Neither proof models supply transients, button bounce, analog propagation or reset recovery/removal. No capacitor or buffer is declared mandatory merely from these omissions. If the assembled circuit behaves poorly, investigate the measured cause before changing the bill of materials.
- Parts prices are historical 2026-10-14 snapshots, not current purchasing quotes. Claude is clearer about purchase-pack prices and includes a 9 V input cable. Codex is stronger on LSSK row traceability and CSV export, but leaves the compatible power-input cable/source outside its displayed wire quantity.
Primary pin/electrical references: TI CD4017B and TI CD4071B / CD4072B.
SystemVerilog style and testbench discipline
Claude’s RTL is generally readable: descriptive names, comments about pin roles, explicit named connections, always_ff for state and aligned output equations. Its posedge checker samples the previous stable cycle deliberately; that is a valid approach. Its nonblocking reset stimulus avoids the usual active-region input race. It needs no arbitrary stimulus delay. These choices deserve credit.
| Current requested convention | Claude | Codex |
|---|
| timeunit / timeprecision | Absent in all nine modules. See F01. | Present in all eleven modules. |
| wire only with continuous declaration assignment | Bare wire declarations in the bench, chip interconnect and TT wrapper. Valid SV, but outside the requested convention. | Applied consistently. |
| Plain net ports and aligned names | Most ports use input/output logic; TT retains eight explicit input/output wire declarations from the template. Port names are generally aligned. | Requested input/output and output logic layout applied. |
| Four-space block indentation; assignment alignment | Mostly good. lab_top has a seven-space assign block; some expected-value declarations are uneven. Continuation/comment alignment is not counted as a functional error. | Mechanically checked across authored HDL. |
| Separate always clock generator | Clock is properly isolated in its own initial/forever block. It does not use the exact requested logic initializer + always form. | Uses logic clk = 1'b0; always # (period / 2) clk = ~ clk;. |
| Delays and negedge | Only clock-generator delay; no falling-edge stimulus. Strongly follows the visible yuri_rules_4.txt guidance. | Uses documented # 1 settling and two justified falling-edge sites to test low-clock behavior. |
| Task bodies / timeout | No task bodies to violate the rule; no cycle watchdog. | No redundant outer task begin/end; all benches have cycle watchdogs. |
The competitor’s warning suppressions name the intended issue (PROCASSINIT and SYNCASYNCNET), and its core runner passes Verilator -Wall without emitted warnings here. This is better than indiscriminately disabling warnings. The three wrapper examples are not included in that supplied runner; their checks above were added by the review.
Codex’s strict modern-time rule has a real compatibility cost: the local old Yosys 0.43 built-in reader rejects it. The documented Slang flow succeeds, but copying the files into an older BGM or Tiny Tapeout flow without changing the frontend can fail. This is an integration limitation, not a reason to silently remove your requested declarations.
